DocumentCode
2521524
Title
A serial physical layer design in RapidIO
Author
Fengfeng, Wu ; Song, Jia ; Wujian, Li ; Yuan, Wang
Author_Institution
Key Lab. of Microelectron. Devices & Circuits (MOE), Peking Univ., Beijing, China
fYear
2010
fDate
15-17 Dec. 2010
Firstpage
1
Lastpage
4
Abstract
RapidIO is an attractive interconnection technology due to its high performance and high reliability. In this paper, the design of serial physical layer in 4x mode with 64-bit inner bus is described in detail. It achieves the goals of link transmission, flow control, error detection and recovery. It is considered to be a feasible and reliable part of SRIO in the high speed embedded system interconnection.
Keywords
embedded systems; error detection; high-speed integrated circuits; integrated circuit interconnections; RapidIO; error detection; error recovery; flow control; high speed embedded system interconnection; link transmission; serial physical layer design; RapidIO; SRIO; error detection and recovery; flow control; physical layer;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of
Conference_Location
Hong Kong
Print_ISBN
978-1-4244-9997-7
Type
conf
DOI
10.1109/EDSSC.2010.5713750
Filename
5713750
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