Title :
Hybrid latch flip-flop with improved power efficiency
Author :
Nedovic, Nikola ; Oklobdzija, Vojin G.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Abstract :
An improved design of a hybrid latch flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and reduces the power consumption and delay of the circuit resulting in a total power-delay-product improvement of about 20%. It also exhibits better soft-clock edge properties compared to the original circuit. This is accomplished by careful design of keeper elements and introducing the feedback path to suppress unnecessary transitions in the circuit. The new design introduces an insignificant area increase
Keywords :
circuit feedback; delays; flip-flops; logic design; low-power electronics; delay reduction; feedback path; hybrid latch flip-flop; keeper elements; power consumption reduction; power efficiency improvement; power-delay-product improvement; precharge technique; soft-clock edge properties; Clocks; Delay; Energy consumption; Feedback circuits; Flip-flops; Laboratories; Latches; Power dissipation; Power engineering computing; State feedback;
Conference_Titel :
Integrated Circuits and Systems Design, 2000. Proceedings. 13th Symposium on
Conference_Location :
Manaus
Print_ISBN :
0-7695-0843-X
DOI :
10.1109/SBCCI.2000.876032
