• DocumentCode
    2521671
  • Title

    Improvements of Fermi-level pinning and NBTI by fluorinated HfO2-CMOS

  • Author

    Chao-Sung Lai ; Wu, Woei-Cherng ; Chiu, Huai-Hsien ; Wang, Jer-Chyi ; Chou, Pai-Chi ; Chao, Tien-Sheng

  • Author_Institution
    Dept. of Electron. Eng., Chang Gung Univ., Taoyuan, Taiwan
  • fYear
    2010
  • fDate
    15-17 Dec. 2010
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Improvement of Fermi-level pinning (FLP) and relaxation of negative-bias-temperature-instability (NBTI) for CMOS without interfacial layers was achieved by fluorine incorporation into HfO2. The driving current capability was increased up to 48% and 45% for n-MOSFET and p-MOSFET, respectively. It´s caused by the oxygen vacancy was blocked by the fluorine incorporated interface and resulted in the suppression of the interfacial oxide growth to achieved thinner effective oxide thickness (EOT). The improvement included the Fermi-level pinning shift from ~0.1eV to ~0.02eV for samples without and with fluorination, respectively. Vth shifts under NBTI stressing were relaxed from positive 350mv to negative 270mv for control and fluorinated samples, respectively. It is due to the Si-F bondings broken under NBTI stressing which the released-fluorine re-incorporate to passivate the HfO2 bulk.
  • Keywords
    CMOS analogue integrated circuits; Fermi level; MOSFET; hafnium compounds; vacancies (crystal); CMOS; HfO2; fermi-level pinning; fluorine; interfacial oxide growth; n-MOSFET; negative-bias-temperature-instability; oxygen vacancy; p-MOSFET; CMOS integrated circuits; Logic gates; Plasmas; Silicon; Stress; Tin;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of
  • Conference_Location
    Hong Kong
  • Print_ISBN
    978-1-4244-9997-7
  • Type

    conf

  • DOI
    10.1109/EDSSC.2010.5713757
  • Filename
    5713757