Post-silicon tuning aware wafer matching algorithm for 3d integration of ICs

This work addresses the problem of wafer-to-wafer matching algorithm for 3D integration of ICs. One critical limitation of the traditional wafer matching methods is that they have attempted to maximize the number of resulting 3D ICs with no faulty (bad) die, but never took into account the time variation between the individual dies in a 3D integrated chip. We show that without considering time variation between dies as well as within wafers during wafer-to-wafer matching, a more aggressive post-silicon tuning is required with increased design cost or a reduced parametric yield of chips is resulted. To overcome this limitation, we propose a post-silicon tuning aware comprehensive wafer matching algorithm to improve the parametric yield of 3D chips. Through experiments with benchmark designs, it is shown that the proposed wafer matching algorithm is able to enhance the parametric yield by up to 8%.