A high parallel-pipelined real-time estimation architecture for MPEG-4 simple profile

A high parallel-pipelined VLSI architecture for MPEG-4 motion estimation is proposed in this paper, searching for the best match to the reference block by full search block matching algorithm to enhance the video quality. It possesses the characteristics of low embedded memory, low clock rate with high accuracy, and flexibility to adapt different search window size, aiming at both mobile applications and high-definition fields. Full search block matching algorithm has been mapped onto this architecture using an optimized processing element array that has the ability to evaluate the motion vectors of CIF video timely at 8 MHZ clock rate with only 5 Kb embedded memory. The proposed architecture has been prototyped, simulated and synthesized for 0.35 μm CMOS technology using FUJITSU CE66 cells. The prototyped architecture consumes 190.3 mW with 3.3 V supply voltage and has core area of 5.52 mm² with 5 layers of metal. It largely improves the performance to more than 33 times faster with only 34.6% more core area cost than the reference motion estimation architecture of MPEG-4 part 9.