An evaluation of 6T and 8T FinFET SRAM cell leakage currents

We present six- and eight-transistor (6T, 8T) FinFET SRAM cell schemes using shorted gate (SG) and low power (LP) FinFET configurations and comprehensively evaluate their leakage currents. FinFETs provide significantly lower leakage current and higher on-current than bulk-CMOS transistors and this allows 8T FinFET SRAM schemes to greatly outperform 8T 32nm CMOS SRAM cells. Reverse-biasing the back gates of the cross-coupled inverter FinFETs reduces leakage current by up to 97%; the largest reduction is obtained with n- and p-back gate biases of -0.2V and V_DD+0.2 V, respectively. This reverse-biasing also minimizes leakage variation due to parameter and temperature variations. Leakage current and read speed are chiefly responsible for SRAM energy consumption. The 6T Low-Power FinFET scheme uses these configurations and has the lowest leakage; however, 8T SRAM schemes perform better than 6T SRAM schemes since leakage current can be reduced by low-power schemes that reverse-bias the cross-coupled inverter FinFET back gates without reducing read speed or read static noise margin. The 8T Low-Power Inverters (LP_INV) scheme has low leakage and performs best with an energy-delay product up to 60% less than the standard 8T Shorted Gate (SG) FinFET scheme and up to 62% less than the best-performing 6T FinFET scheme.