Title :
FDSOI SRAM cells for low power design at 22nm technology node
Author :
Linbin Chen ; Lombardi, Floriana ; Jie Han
Author_Institution :
Electr. & Comput. Eng. Dept., Northeastern Univ., Boston, MA, USA
Abstract :
The silicon-on-insulator (SOI) MOSFET is considered as an alternative to the bulk (silicon-based MOSFET in CMOS circuits for applications requiring low-voltage and low-power operation. Fully depleted SOI (FDSOI) benefits from a high current driven ability; so, this technology preserves advantageous features, such as steep sub threshold characteristics and small short channel effects. This paper presents a comprehensive assessment of different SRAM (Static Random Access Memory) cells utilizing different numbers of transistors (i.e. 8 and 9). These cells are evaluated by HSPICE for different performance metrics (such as write/read delay, stability, critical charge, power consumption and tolerance to voltage threshold variation) at the 22nm technology node.
Keywords :
CMOS memory circuits; SRAM chips; elemental semiconductors; integrated circuit design; low-power electronics; silicon-on-insulator; CMOS circuits; FDSOI SRAM cells; HSPICE; SOI MOSFET; Si; critical charge; current driven ability; fully-depleted SOI; low-power design; low-voltage low-power operation; power consumption; silicon-on-insulator MOSFET; size 22 nm; small-short channel effects; static random access memory cell; steep sub threshold characteristics; voltage threshold variation; write-read delay; CMOS integrated circuits; Delays; MOSFET; Power demand; SRAM cells; FDSOI; Low Static Power; SNM; SRAM Cell;
Conference_Titel :
Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on
Conference_Location :
College Station, TX
Print_ISBN :
978-1-4799-4134-6
DOI :
10.1109/MWSCAS.2014.6908468
