On design of low-voltage CMOS current amplifiers

The paper presents a new approach to design of current amplifiers. The amplifying cell core represents the connection of three transistors: a bias transistor and a differential pair. The bias transistor sets the distribution of currents in the differential pair. When an external current signal is applied to the core input the outputs of the differential pair provide two complementary current signals. The loading of the differential pair by a current mirror provides current conversion, and, depending on the current mirror orientation, one obtains a positive or negative current amplifying stage. These stages can be directly cascaded to obtain multistage high current gain amplifier. The gain of multistage amplifier may be stabilized using an external resistive current divider or external differential pair used as current distributor. The paper considers static and dynamic characteristics of the amplifying stages, and the frequency response of the two-stage amplifier. The amplifier was designed for 45 nm CMOS technology, the simulation was done using Cadence. The results of calculations and simulations are in a reasonable agreement.