DocumentCode
2522126
Title
Design and optimization of a novel SOI LDMOS structure using PIN junction
Author
Zhu, Mingda ; Wang, Juncheng ; Du, Gang
Author_Institution
Inst. of Microelectron., Peking Univ., Beijing, China
fYear
2010
fDate
15-17 Dec. 2010
Firstpage
1
Lastpage
4
Abstract
A novel SOI LDMOS (Lateral Double Diffused MOSfet) structure substituting the PN junction between channel region and drift region with PIN junction is presented in this paper. On-state and off-state characteristics of this device are investigated by two dimensional simulation using Dessis. This novel device has higher breakdown voltage with the same drift length compared to conventional device. The effects of intrinsic region length on device characteristics are further investigated.
Keywords
MOSFET; electric breakdown; p-i-n diodes; semiconductor device models; Dessis; LDMOS structure; PIN junction; SOI; breakdown voltage; design and optimization; two dimensional simulation; Electric breakdown; LDMOS; PIN junction; breakdown voltage; on-state voltage drop;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of
Conference_Location
Hong Kong
Print_ISBN
978-1-4244-9997-7
Type
conf
DOI
10.1109/EDSSC.2010.5713781
Filename
5713781
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