High-speed low-power decimation filter for wideband Delta-Sigma ADC

This paper discusses the design of high-speed low-power decimation filter for wideband Delta-Sigma ADC. It presents a low power decimation filter with programmable decimation ratios (32, 64 and 128) and sampling rates (624MHz, 312MHz and 208MHz) for LTE application. The decimation filter has five different operating modes and consists of three sinc filters, two halfband filters and a FIR filter. It uses power efficient polyphase decomposition filter with a wise clock distribution approach to minimize power consumption. The decimation filter is implemented in 130 nm CMOS process, which consumes 0.46 × 0.46 mm² cell area. Simulation results show that when Sigma-Delta modulator output sampling frequency is 624MHz, 312MHz and 208MHz, it consumes less than 4.6mW, 2.3mW and 1.5mW from 1.2V supply respectively. In addition, they all achieve a Signal-to-Noise Ratio of 69dB over the signal bandwidth.