Variability investigation of gate-all-around silicon nanowire transistors from top-down approach

Author

Huang, R. ; Wang, R.S. ; Zhuge, J. ; Yu, T. ; Ai, Y.J. ; Fan, C. ; Pu, S.S. ; Zou, J.B. ; Huang, X. ; Wang, Y.Y.

Author_Institution

Inst. of Microelectron., Peking Univ., Beijing, China

fYear

2010

fDate

15-17 Dec. 2010

Firstpage

1

Lastpage

4

Abstract

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices. This paper discusses the process impact on nanowire LER/LWR, as well as the impact of 2D nanowire LER on performance variation and degradation. And it is found that SNWTs, which is immune to channel RDF(random dopant fluctuation), exhibit SDE-RDF which is enhanced by diameter-dependent annealing. In addition, the different impacts of the experimentally extracted variation sources in SNWTs on the threshold voltage and on current flucturation is discussed, as well as the variability impact on SNWT based SRAM cells compared with planar SRAM cells.

Keywords

SRAM chips; nanowires; silicon; transistors; SRAM cells; gate-all-around silicon nanowire transistors; random dopant fluctuation; top-down approach; variability investigation; Annealing; Integrated circuits; Three dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-9997-7

Type

conf

DOI

10.1109/EDSSC.2010.5713789

Filename

5713789