• DocumentCode
    252239
  • Title

    Optimization of a dot product accelerator

  • Author

    Biswas, Arijit

  • Author_Institution
    Cisco Syst., San Jose, CA, USA
  • fYear
    2014
  • fDate
    3-6 Aug. 2014
  • Firstpage
    619
  • Lastpage
    622
  • Abstract
    Vector dot product is an important computation which needs hardware accelerators. We present an optimized accelerator chip that has larger capacity than our prior designs. This design can compute product for 10000 component vectors within 1000 clock cycles, with average being 80 cycles. Our design has superior speed compared to other accelerators.
  • Keywords
    clocks; integrated circuit design; microprocessor chips; optimisation; clock cycles; component vectors; design; dot product accelerator; hardware accelerators; optimization; optimized accelerator chip; vector dot product; Clocks; Computer aided manufacturing; Computer architecture; Hardware; Optimization; Testing; Vectors; Dot product coprocessor; parallelization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on
  • Conference_Location
    College Station, TX
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-4799-4134-6
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2014.6908491
  • Filename
    6908491
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=252239