Towards integrated circuit thermal profiling for reduced power consumption: Evaluation of distributed sensing techniques

Reducing the power consumption in integrated circuits will require the use of several techniques, many of which depends on accurate on-chip temperature measurement. Simultaneously, power consumption can be reduced by using smaller integration scales of System-on-Chip (SoC). This will require a comprehensive solution to the ensuing more frequent problems of reliability-related events. This paper introduces the use of an on-chip sensor network to monitor reliability-related parameter and to adapt local chip components to ensure continuing efficient operation with reduced power consumption. The sensor network design is constrained to present a negligible footprint in terms of the chip internal bandwidth use, power consumption and number and area of integrated components. In this context, this paper considers the problem of monitoring the time evolution of the complete chip thermal profile. Different distributed sensing and source compression schemes that leverage on the physical properties of heat propagation and networking of sensors are evaluated in terms of bandwidth and power consumption saving potential. Simulation results show the potential for these techniques to provide useful savings in on-chip communication bandwidth. Considering strict implementation complexity constraints, distributed source coding through binning is the evaluated technique that shows best performance.