A system-level design approach for SDR-based MPSoC in LTE baseband processing

This paper presents a system-level design approach from application perspective for an SDR based MPSoC (Multi-Processor System-on-Chip) in LTE baseband processing. Based on a quantitative measurement, a 0-1 knapsack model is proposed for hardware-software partition to enhance flexibility by replacing ACC (ACCelerator) with ASIP (Application-Specific Instruction-set Processor). In order to reduce the power consumption of ASIP, a two-level frequency requirement is formed according to the characteristics of baseband processing. Under this approach, the complex symbol based calculation can be all realized on ASIP and the same MPSoC can serve the LTE-A application by software programming. Moreover, the frequency of the ASIPs can be scaled down according to the requirement to get a power reduction from 6% to 90%.