Dynamic Partitioned Global Address Spaces for power efficient DRAM virtualization

Dynamic Partitioned Global Address Spaces (DPGAS) is an abstraction that allows for quick and efficient remapping of physical memory addresses within a global address space, enabling more efficient sharing of remote DRAM. While past work has proposed several uses for DPGAS [1], the most pressing issue in today´s data centers is reducing power. This work uses a detailed simulation infrastructure to study the effects of using DPGAS to reduce overall data center power through low-latency accesses to “virtual” DIMMs. Virtual DIMMs are remote DIMMs that can be mapped into a local node´s address space using existing operating system abstractions and low-level hardware support to abstract the DIMM´s location from the application using it. By using a simple spill-receive memory allocation model, we show that DPGAS can reduce memory power from 18% to 49% with a hardware latency of 1 to 2 μs in typical usage scenarios. Additionally, we demonstrate the range of scenarios where DPGAS can be realized over a shared 10 Gbps Ethernet link with normal network traffic.