Bulk and FDSOI SRAM resiliency to radiation effects

Author

Calienes, Walter ; Reis, R. ; Anghel, Costin ; Vladimirescu, Andrei

Author_Institution

Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil

fYear

2014

fDate

3-6 Aug. 2014

Firstpage

655

Lastpage

658

Abstract

With the increasing density of transistors in advanced technology nodes, the radiation is an ongoing problem affecting the contents of memory cells. This paper presents the simulation results of radiation immunity for two different memory cell technologies: 32nm Bulk CMOS and 28nm FDSOI. The effect of Single-Event Upset (SEU) caused by the heavy ion impact with different Linear Energy Transfer characteristic (LET) is analyzed. A 32nm bulk 6T-SRAM cell is at least 6 times less resilient to heavy ion strikes than the 28nm FDSOI one.

Keywords

CMOS memory circuits; SRAM chips; radiation hardening (electronics); silicon-on-insulator; FDSOI SRAM resiliency; LET; SEU; advanced technology nodes; bulk 6T-SRAM cell; bulk CMOS SRAM; linear energy transfer characteristic; memory cell technology; radiation effects; radiation immunity; single-event upset effect; size 28 nm; size 32 nm; Computational modeling; Equations; Integrated circuit modeling; Mathematical model; Semiconductor process modeling; Silicon; Transistors; Bulk transistor; FDSOI transistor; Heavy Ion; Microelectronics; Radiation Effects; Simulation; Single-Event Upset;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on

Conference_Location

College Station, TX

ISSN

1548-3746

Print_ISBN

978-1-4799-4134-6

Type

conf

DOI

10.1109/MWSCAS.2014.6908500

Filename

6908500