Title :
Design and evaluation of a fault-tolerant adaptive router for parallel computers
Author :
Yoshinaga, Tsutomu ; Hosogoshi, Hiroyuki ; Sowa, Masahiro
Author_Institution :
Graduate Sch. of Inf. Syst., Electro-Commun. Univ., Tokyo, Japan
Abstract :
In this paper, we propose a design methodology for fault-tolerant adaptive routers for parallel and distributed computers. The key idea of our method is integrating minimal and non-minimal routing that is supported by independent virtual channels (VCs). Distinguishing the routing functions for each set of VCs simplifies the design of fault-tolerant algorithms. After describing the method, we show an application of a routing algorithm for two-dimensional mesh and torus networks. This algorithm, called Detour-NF, supports three routing modes: deterministic, minimal fully adaptive and non-minimal fault-tolerant operations. We also discuss the hardware cost and operational speed of minimal and non-minimal routers based on our design, which uses hardware description language (HDL). Communication performance and fault-tolerance are demonstrated by an HDL simulation. The experimental results show that supporting both minimal and non-minimal routing modes is advantageous for high-bandwidth and low-latency communication, as well as fault-tolerance.
Keywords :
circuit simulation; fault tolerant computing; hardware description languages; network routing; parallel processing; performance evaluation; Detour-NF; communication performance; deterministic routing; distributed computers; fault-tolerance; fault-tolerant adaptive router; fault-tolerant routing; hardware cost; hardware description language; hardware design; independent virtual channels; low-latency communication; minimal fully adaptive routing; nonminimal routing; operational speed; parallel computers; torus networks; two-dimensional mesh; Algorithm design and analysis; Concurrent computing; Costs; Design methodology; Distributed computing; Fault tolerance; Hardware design languages; Routing; Switches; Telecommunication traffic;
Conference_Titel :
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003
Print_ISBN :
0-7695-2019-7
DOI :
10.1109/IWIA.2003.1262787