A 3.45–4.22 GHz PLL frequency synthesizer with constant loop bandwidth for WLAN applications

A fully integrated phase-locked loop (PLL) frequency synthesizer for WLAN applications is designed in a 0.13-μm CMOS process. In order to make the loop bandwidth constant across the whole operating frequency range, a switched varactor array based LC-VCO is used to achieve a low K_VCO variation, the charge pump current is programmed proportional to division ratio, and the variation on LPF resistance is cancelled by a matched reference resistance in a band-gap. By combination of these techniques, a constant loop bandwidth is achieved over the entire output frequency range. The proposed PLL attains less than ± 4% variation in loop bandwidth over an operating frequency range from 3.45 to 4.22 GHz. The chip consumes 21.1 mW of power while occupying an area of 0.88 mm².