Novel buck converter architectures for large step-down conversion ratio

Ultra low duty-cycle clock signal is required in buck converters with large step-down voltage conversion ratio. Given the maximum achievable rise and fall time as well as the minimum ON time of the transistors, this sets a maximum limit on the operating frequency. Different buck converter architectures are proposed to achieve the same voltage conversion ratio with a larger duty cycle. Therefore, the constraints on the minimum transistor ON time and the maximum operating frequency are relaxed. The proposed converters are completely independent on mutual coupling and, as a consequence, they do not suffer from any leakage inductance and do not need any protection or clipping circuits. The analysis produces the relation between the duty-cycle and the voltage gain and shows how much the enhancements are. The simulation results confirm the analysis.