Title :
Expression synthesis in process networks generated by LAURA
Author :
Zissulescu, C. ; Kienhuis, B. ; Deprettere, E.
Author_Institution :
Leiden Inst. of Adv. Comput. Sci., Netherlands
Abstract :
The COMPAAN/LAURA (Stefanov et al., 2004) tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application as a process network in which the control is parameterized and distributed. This control is given as parameterized polytopes that are expressed in terms of pseudo-linear expressions. These expressions cannot always be mapped efficiently onto hardware as they contain multiplication and integer division operations. This obstructs the data flow through the processes. Therefore, we present in this paper the expression compiler that efficiently maps pseudo-linear expressions onto a dedicated hardware data-path in such a way that the distributed and parameterized control never obstructs the data flow through processors. This compiler employs techniques like number theory axioms, method of difference, and predicated static single assignment code.
Keywords :
data flow computing; field programmable gate arrays; mathematics computing; program compilers; COMPAAN; FPGA; LAURA; Matlab; data flow; distributed control; expression compiler; expression synthesis; method of difference; nested loop application; number theory axiom; parameterized control; parameterized polytope; predicated static single assignment code; process network; pseudolinear expression; Application software; Clocks; Computer science; Distributed control; Electronic mail; Field programmable gate arrays; Hardware; Intelligent networks; Network synthesis; Program processors;
Conference_Titel :
Application-Specific Systems, Architecture Processors, 2005. ASAP 2005. 16th IEEE International Conference on
Conference_Location :
Samos, Greece
Print_ISBN :
0-7695-2407-9
DOI :
10.1109/ASAP.2005.34