• DocumentCode
    2523581
  • Title

    Multiply-accumulate architecture for a special class of optimal extension fields

  • Author

    Sanu, Moboluwaji O. ; Swartzlander, Earl E., Jr.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
  • fYear
    2005
  • fDate
    23-25 July 2005
  • Firstpage
    134
  • Lastpage
    139
  • Abstract
    Finite field arithmetic is useful in the implementation of error-correcting codes as well as cryptographic protocols. Large finite field numbers are particularly important in the implementation of elliptic curve cryptography. This paper presents a multiply-accumulate architecture for multipliers over a special class of type II optimal extension fields (OEFs). Type II OEFs are Galois fields GF (pm) with p a pseudo-Mersenne prime of the form p = 2n $c, where c is "small", and an irreducible binomial of the form f (z) = zm $2 exists over GF (p). The Type II OEF multiplier presented uses merged arithmetic to combine multiple multiply and addition operations together. Unlike previous work, the multiplier also performs subfield and extension field reduction in parallel for this class of finite fields. Though the multiplier design requires large silicon area for practical implementation, it obviates the need for performing subfield and extension field reduction separately, thereby reducing the overall delay.
  • Keywords
    Galois fields; cryptography; digital arithmetic; Galois field; addition operation; elliptic curve cryptography; extension field reduction; finite field arithmetic; multiplier design; multiply operation; multiply-accumulate architecture; optimal extension field; pseudo-Mersenne prime; subfield field reduction; type II OEF multiplier; Computer architecture; Cryptographic protocols; Delay; Digital arithmetic; Elliptic curve cryptography; Error correction codes; Galois fields; Integral equations; Polynomials; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application-Specific Systems, Architecture Processors, 2005. ASAP 2005. 16th IEEE International Conference on
  • ISSN
    2160-0511
  • Print_ISBN
    0-7695-2407-9
  • Type

    conf

  • DOI
    10.1109/ASAP.2005.46
  • Filename
    1540377