Instruction set architecture enhancements for video processing

This paper presents some of the enhancements to the TriMedia instruction set architecture (ISA), as supported by the TM3270 media-processor. We show how the new operations are used to optimize the individual MPEG2 encoder kernels. Furthermore, we quantify the contribution of these kernels to overall MPEG2 encoder performance. We introduce two-slot operations, collapsed load operations with interpolations, and new multiplication operations. The encoder´s texture pipeline for a bi-directionally predicted 8×8 block is performed in 358 VLIW instructions. MPEG2 encoding at CIF resolution at 25 frames per second is achieved within 33.5 MHz of processor performance.