Robust subthreshold 7T-SRAM cell for low-power applications

Author

Moradi, Farshad ; Madsen, Jens K.

Author_Institution

Dept. of Eng., Aarhus Univ., Aarhus, Denmark

fYear

2014

fDate

3-6 Aug. 2014

Firstpage

893

Lastpage

896

Abstract

In this paper, a novel 7T-SRAM cell for ultra-low power applications is proposed. The proposed SRAM cell is fully functional at subthreshold voltages down to VDD_min=200mV. In this technique, separate read/write bitlines and wordlines are used that makes read and write operation independent. The 7T-SRAM cell proposed in this paper, improves static read noise margin, write margin, and write time by 2.2X, 27%, and 6% in comparison to the standard 6T-SRAM cell. The 7T-SRAM cell proposed in this paper, improves write margin of the conventional 7T-SRAM cell, as well. The proposed 7T-SRAM cell is designed in 65nm CMOS technology.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit design; low-power electronics; CMOS technology; conventional 7T-SRAM cell; read operation; read-write bitlines; robust subthreshold 7T-SRAM cell; size 65 nm; static read noise margin; subthreshold voltage; ultralow-power application; voltage 200 mV; wordlines; write operation; write time; Computer architecture; Noise; SRAM cells; Standards; Transistors; Writing; CMOS; Read Static Noise Margin; SRAM; Write Margin;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on

Conference_Location

College Station, TX

ISSN

1548-3746

Print_ISBN

978-1-4799-4134-6

Type

conf

DOI

10.1109/MWSCAS.2014.6908559

Filename

6908559