Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology

Author

Innocenti, Jordan ; Welter, Loic ; Julien, F. ; Lopez, L. ; Sonzogni, Jacques ; Niel, S. ; Regnier, A. ; Paire, Emmanuel ; Labory, Karen ; Denis, Eric ; Portal, J.-M. ; Masson, P.

Author_Institution

STMicroelectron. Rousset, Rousset-Peynier, France

fYear

2014

fDate

3-6 Aug. 2014

Firstpage

897

Lastpage

900

Abstract

This paper describes different solutions to decrease dynamic consumption of circuits processed on an embedded non-volatile memories CMOS 80 nm technology. Up to 25 % in dynamic power reduction is demonstrated without degrading performances and static leakages of devices and above all, with full DMR compliancy. Ring oscillator designs are used to estimate the dynamic power gain, comparing new development process (B) to reference process (A) currently in use in manufacturing.

Keywords

CMOS memory circuits; oscillators; random-access storage; CMOS embedded nonvolatile memory technology; design optimization; development process; device static leakages; dynamic power gain estimation; dynamic power reduction; full-DMR compliancy; process optimization; reference process; ring oscillator design; size 80 nm; CMOS integrated circuits; CMOS technology; Capacitance; Logic gates; MOSFET; Ring oscillators; CMOS inverter; Low power; carriers mobility enhancement; dynamic/static power; ring oscillator; standard cell;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on

Conference_Location

College Station, TX

ISSN

1548-3746

Print_ISBN

978-1-4799-4134-6

Type

conf

DOI

10.1109/MWSCAS.2014.6908560

Filename

6908560