An advanced self-aligned BiCMOS technology for high performance 1-megabit ECL I/O SRAMs

Author

Burger, W.R. ; Lage, C. ; Davies, T. ; DeLong, M. ; Haueisen, D. ; Small, J. ; Huglin, G. ; Landau, B. ; Whitwer, F. ; Bastani, B.

Author_Institution

Nat. Semicond. Corp., Puyallup, WA, USA

fYear

1989

fDate

3-6 Dec. 1989

Firstpage

421

Lastpage

424

Abstract

An advanced self-aligned BiCMOS technology has been developed for high-performance 1-Mb ECL I/O SRAMs (emitter-coupled-logic input/output static RAMs). The 0.8 mu m technology features include an advanced, fully recessed oxide isolation, a silicided polysilicon local interconnect scheme, two levels of polysilicon, and two levels of metal with tungsten plugs. These process features combine to produce MOS gate delays in the 100-ps range and bipolar transistors with F/sub T/ of 15 GHz. The manufacturability of the technology has been demonstrated by the successful fabrication of a scaled 256 K ECL I/O SRAM.<>

Keywords

BIMOS integrated circuits; SRAM chips; emitter-coupled logic; integrated circuit technology; integrated memory circuits; 0.8 micron; 1 Mbit; 100 ps; 15 GHz; ECL I/O SRAMs; MOS gate delays; bipolar transistors; fully recessed oxide isolation; interconnect scheme; process features; self-aligned BiCMOS technology; BiCMOS integrated circuits; Bipolar transistors; CMOS technology; Integrated circuit interconnections; Isolation technology; MOS devices; MOSFETs; Optimized production technology; Random access memory; Tungsten;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1989.74312

Filename

74312