A novel flexible 16-core MP-SoC architecture based on parallel skeletons for image processing applications

For many image processing systems, the computing power required can not be provided by a single sequential processor, this is why many designers appeal to multiprocessor systems (parallelism). This article proposes an original flexible MP-SoC (Multi-Processors System on Chip) architecture for image processing applications. Developing processors network systems tailored to a particular application domain is critical and design-time consuming in order to achieve high-performance customized solutions. This paper introduces a 16-core MP-SoC ASIC with a software configuration. In particular, each tile of the network can configure its communication links depending on the most relevant overall parallelism scheme for a targeted application. Results are shown in term of power, area and timing performance for a 65 nm CMOS technology ASIC design. A case study (grey scale histogram analyzes) is presented to illustrate the proposed flexible MP-SoC design methodology and enables to focus on architecture exploration, instantiated scheme of parallelization and timing performance.