Leakage and delay analysis in FinFET array multiplier circuits

This paper investigates the performance of array multipliers utilizing FinFET models for the following feature sizes: 20nm, 16nm, 14nm, 10nm and 7nm. Using basic array multiplier topology and standard cell 28 transistor full adders, the static power and delay of FinFET array multiplier circuits were investigated using HSPICE and low power Predictive Technology Models (PTM). Simulation results show an increase in static power and a decrease in delay as the feature size decreases. Comparisons between array multiplier sizes show nonlinear increases in both static power and delay as size increases from 4×4 up to 16×16. The results obtained in this research will provide a starting point for the design and analysis of more complex FinFET based arithmetic circuit designs.