DocumentCode
2523805
Title
Zippy - a coarse-grained reconfigurable array with support for hardware virtualization
Author
Plessl, Christian ; Platzner, Macro
Author_Institution
Comput. Eng. & Networks Lab., ETH Zurich, Switzerland
fYear
2005
fDate
23-25 July 2005
Firstpage
213
Lastpage
218
Abstract
This paper motivates the use of hardware visualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder.
Keywords
reconfigurable architectures; virtual machines; ADPCM decoder; Zippy; coarse-grained reconfigurable array; hardware virtualization; multicontext hybrid CPU; Application virtualization; Computer architecture; Computer networks; Computer science; Concrete; Decoding; Hardware; Platform virtualization; Reconfigurable architectures; Virtual machining;
fLanguage
English
Publisher
ieee
Conference_Titel
Application-Specific Systems, Architecture Processors, 2005. ASAP 2005. 16th IEEE International Conference on
ISSN
2160-0511
Print_ISBN
0-7695-2407-9
Type
conf
DOI
10.1109/ASAP.2005.69
Filename
1540388
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