Data retention voltage analysis of various low-power SRAM topologies

In this paper, we analyze and compare five different low-power SRAM cell topologies in terms of their data retention voltages (DRV). The circuit simulation and analysis was carried out using HSPICE with the 45 nm, 32 nm, and 22 nm low-power Predictive Technology Model (PTM) transistor models by setting the SRAM cells to an initial state and bringing the supply voltage down for different standby voltages. Based on these results, the standard 6T SRAM cell provides the lowest DRV out of all of the SRAM cells in this study at the 45 nm and 32 nm process nodes, but the 7T, 8T, and 10T SRAM cells provide better DRV performance at the 22 nm process node. These results give a first look at the effects that SRAM cell topology can have on DRV, and provide a starting point for future research into ultra low-power memory design.