Comparison of 130 nm technology 6T and 8T SRAM cell designs for Near-Threshold operation

Power consumption is an important aspect of almost any electrical device design. Near-Threshold Computing (NTC) is a voltage scaling technique that makes it possible to reduce the power consumption of CMOS devices with the cost of speed and reliability. We are using NTC to design low-power cache memory circuit for a low-performance sensor-based system. Caches consume noteworthy portions of power and area of this kind of systems, and therefore reducing their power consumption has a meaningful impact on the overall power consumption of the whole system. In this paper, 8T SRAM and 6T SRAM memory cells are compared in order to establish guidelines for choosing SRAM cell constructions for NTC systems. 8T SRAM is traditionally concerned as a more reliable memory cell, but we have managed to design 6T SRAM which executes read operation with an acceptable reliability; read being the most vulnerable operation of conventional 6T SRAM cell. Also, our 6T SRAM cell has 31% smaller area and smaller power consumption.