On estimations for compiling software to FPGA-based systems

This paper presents recent advances in a compiler infrastructure to map algorithms described in a Java subset to FPGA-based platforms. We explain how delays and resources are estimated to guide the compiler through scheduling and temporal partitioning. The compiler supports complex analytical models to estimate resources and delays for each functional unit. The paper presents experimental results for a number of benchmarks. Those results also arise a question when performing temporal partitioning: shall we try to group as many computational structures in the same configuration or shall we have several configurations?.