An improved high speed low noise CMOS image sensor

We present an analog CMOS image sensor design as an improvement to the design presented in previous work [1]. Negative feedback is applied to the readout of each row-shared circuit to augment the current driving capability and thereby reduce the settling time during the pixel readout operation. The current sensing and amplification is implemented using a current amplifier utilizing symmetric current mirrors which improves the bandwidth and hence the readout speed of the image sensor while maintaining minimum power consumption. In addition, faster settling time reduces the time between consecutive CDS samples, which in turn helps to attenuate the 1/f noise introduced by the in-pixel source-follower transistor of a standard active pixel sensor (APS) design. We demonstrate a speed improvement of five times over the standard APS design. Further speed improvement is readily achievable by increasing the current gain of the amplifier at the cost of power and area. The circuit analysis, design considerations, and simulation results of the proposed CMOS image sensor in a standard 0.35μm technology are presented here.