Defect-oriented test quality assessment using fault sampling and simulation

Author

Goncalves, F.M. ; Santos, M.B. ; Teixeira, I.C. ; Teixeira, J.P.

Author_Institution

IST, INESC, Lisbon, Portugal

fYear

1998

fDate

18-23 Oct 1998

Firstpage

35

Lastpage

42

Abstract

The purpose of this paper is to present a novel methodology for the estimation of VLSI products defect level, or reject rates, in the IC design environment. A new defect-oriented (DO) fault extraction and stratified sampling technique, implemented in an extraction tool, lobs, is used with a novel DO fault simulation tool, veriDOFS, which uses a commercial Verilog simulation tool. The proposed methodology allows the evaluation of DL values with limited confidence intervals, using reduced fault samples. Results, for a s38417 benchmark circuit (almost 100,000 transistors and over 140,000 extracted bridging defects) lead to test quality validation with 2,000 sampled faults

Keywords

VLSI; design for testability; digital simulation; electronic engineering computing; fault simulation; integrated circuit design; integrated circuit testing; signal sampling; IC design environment; VLSI products defect; Verilog simulation tool; bridging defects; defect-oriented test; extraction tool; fault extraction; fault sampling; fault simulation tool; lobs; reject rates; s38417 benchmark circuit; simulation; stratified fault sampling; stratified sampling; test quality validation; veriDOFS; Circuit faults; Circuit simulation; Circuit testing; Integrated circuit modeling; Integrated circuit testing; Quality assessment; Sampling methods; Test pattern generators; US Department of Transportation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1998. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-5093-6

Type

conf

DOI

10.1109/TEST.1998.743134

Filename

743134