• DocumentCode
    2524177
  • Title

    Sampling optimization for macro-modeling interconnect parasitic extraction

  • Author

    Abdellatif, A. Shehata ; El Rouby, Alaa B. ; Abdelhalim, M.B. ; Khalil, A.H.

  • Author_Institution
    Elec. & Comm. Dept., Cairo Univ., Giza, Egypt
  • fYear
    2010
  • fDate
    26-28 April 2010
  • Firstpage
    1482
  • Lastpage
    1487
  • Abstract
    Parasitic extraction is a critical task for modern nano scale semiconductor circuits which are characterized by high speed, small feature size and dense layout. Among the available extraction methodologies is the macro-modeling, which is based on dividing the circuit into smaller parts, then matching those smaller parts to a pre-defined model library whose parasitics are known. In the macro-modeling method, building the predefined model library goes into a number of stages; a major stage of them is the sampling stage, where we calculate the parasitic associated with the predefined models at a set of selected geometries (samples). Those samples are, then, used to build the model library by fitting them to a model equation. In this paper we are focusing on optimizing the sampling stage of the macro-modeling method for interconnect parasitic extraction. Herein, we optimize (minimize) the sample size where a graphically inspired method is introduced to define the minimum sample size for complex non-linear model equation mathematically. This method also addresses the impact of the data set uncertainty on the minimum required sample size. Then, we introduce a method for optimizing the distributing of those minimum required sample size. This sample distribution method, is based on Latin hypercube hybridization, optimizes inter-sample distances and correlations concurrently.
  • Keywords
    integrated circuit interconnections; integrated circuit packaging; nanotechnology; optimisation; sampling methods; Latin hypercube hybridization; complex nonlinear model equation; graphically inspired method; interconnect parasitic extraction; macro-modeling method; nanoscale semiconductor circuits; predefined model library; sample distribution method; sampling optimization; Data mining; Geometry; Integrated circuit interconnections; Libraries; Mathematical model; Nonlinear equations; Optimization methods; Sampling methods; Solid modeling; Uncertainty; Design of Experiment; Latin Hypercube Design; Macro modeling; Parasitic Extraction;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    MELECON 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference
  • Conference_Location
    Valletta
  • Print_ISBN
    978-1-4244-5793-9
  • Type

    conf

  • DOI
    10.1109/MELCON.2010.5476241
  • Filename
    5476241