Input-aware statistical timing analysis for VLSI delay test and average design

Nanoscale VLSI systems are subject to an ever increasing performance variability, which hinders performance scaling and increases verification complexity. In this paper, we study an often neglected source of performance variability, namely logic inputs or system workload. We present input-aware statistical timing analysis, which gives not only critical path delays but also critical path activating input patterns and critical path activation probabilities. We further present its applications in delay test for improved fault coverage and better-than-worst-case design for improved average performance.