DocumentCode :
252436
Title :
LEMA: A tool for the formal verification of digitally-intensive analog/mixed-signal circuits
Author :
Fisher, Andrew N. ; Batchu, Satish ; Jones, Ken ; Kulkarni, Devdatta ; Little, Scott ; Walter, Dennis ; Myers, Chris J.
Author_Institution :
Univ. of Utah, Salt Lake City, UT, USA
fYear :
2014
fDate :
3-6 Aug. 2014
Firstpage :
1017
Lastpage :
1020
Abstract :
The increasing integration of analog/mixed-signal (AMS) circuits into system designs has further complicated an already difficult verification problem. Recently, formal verification, which has been successful in the purely digital domain, has made some in-roads in the AMS domain. This paper describes one such formal verification tool for AMS circuits, LEMA. In particular, LEMA is capable of generating a formal model from simulation traces that, when coupled with a formal property provided in our new property language, can be model checked with one of three model checkers within LEMA. This paper briefly describes the capabilities of the LEMA AMS verification tool flow.
Keywords :
circuit analysis computing; formal verification; integrated circuit design; mixed analogue-digital integrated circuits; AMS circuits; LEMA AMS verification tool flow; digitally-intensive analog-mixed-signal circuits; formal verification; property language; simulation traces; system designs; Clocks; Delays; Generators; Integrated circuit modeling; Voltage control; Voltage-controlled oscillators; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on
Conference_Location :
College Station, TX
ISSN :
1548-3746
Print_ISBN :
978-1-4799-4134-6
Type :
conf
DOI :
10.1109/MWSCAS.2014.6908590
Filename :
6908590
Link To Document :
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