Reduced clock harmonic distortion technique in maximum tunable switched-R-MOSFET-C filters

In this paper a method to reduce the harmonic distortion caused by the switching operation in switched-R-MOSFET-C filters is presented. The technique is demonstrated through simulations and backed by analytical expressions for first order active RC and second order biquad filters; the improvement in clock distortion is presented and compared with previously reported architectures. The proposed harmonic cancellation technique shows an improvement of more than 33 dB over previous architectures without compromising the tuning range.