Double-sampled wideband delta-sigma ADCs with shifted loop delays

Double sampling for delta-sigma ADCs is an effective technique for wideband and low-power data conversion. This paper proposes a double-sampled delta-sigma modulator topology with shifted loop delays. Compared with existing double-sampled modulators, this architecture implements the inherent quantization delay by shifting the delay from the last integrator to the quantizer, and it relaxes critical timing for DEM by shifting the delay from the first integrator to the feedback path. Also, by inserting one more delay in the signal path, the proposed modulator keeps the low-distortion property. To verify the effectiveness of the proposed topology, a second-order double-sampled delta-sigma modulator was designed and simulated.