Title :
A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC
Author :
Gupta, Amit Kumar ; Nagaraj, Kanthi ; Viswanathan, T.R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas, Austin, TX, USA
Abstract :
In this paper we present the design of a Nyquist rate VCO based ADC implemented in 65nm CMOS process. The design achieves a peak SNDR of 63.7dB and a SFDR of 76dB in 10MHz bandwidth while consuming 1.1mW of power and occupying only 0.07mm2 of active area. The pseudo-differential VCO implemented in the prototype achieves better than 9-bits linearity with the overall ADC linearity better than 12 bits. The figure of merit (FoM) is 44fJ/conversion and should improve when implemented in more advanced processes.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; time-digital conversion; voltage-controlled oscillators; CMOS process; FoM; Nyquist rate VCO based ADC; bandwidth 10 MHz; hybrid voltage-time domain ADC; power 1.1 mW; pseudodifferential VCO; size 65 nm; word length 9 bit; Clocks; Delays; Linearity; Power demand; Prototypes; Radiation detectors; Voltage-controlled oscillators; ADC; VCO; reference refreshing; reference scaling;
Conference_Titel :
Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on
Conference_Location :
College Station, TX
Print_ISBN :
978-1-4799-4134-6
DOI :
10.1109/MWSCAS.2014.6908599
