Title :
Modular logic built-in self-test for IP cores
Author :
Rajski, J. ; Tyszer, Jerzy
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR, USA
Abstract :
The paper presents a new modular logic BIST architecture for intellectual property (IF) cores and block-oriented design methodology. The scheme involves two-step development process: design and analysis of BIST-ready IP cores and system integration. A BIST-ready core has inserted scan chains, test points, a repeater with phase shifter to perform serial to parallel conversion of test vectors, and a space-time test-response compactor. It is also simulated to determine its fault coverage and signature for a specified configuration of BIST hardware. Particulars of a method to compute the composite signature for the whole design based on signatures representing individual cores are presented altogether with a new technique to expand test vectors. At the system ASIC level, the paper demonstrates how multiple cores can be seamlessly integrated and then tested in exactly the same manner as they were analyzed by sharing the same BIST controller
Keywords :
application specific integrated circuits; automatic testing; built-in self test; design for testability; industrial property; integrated circuit testing; modules; repeaters; ASIC; BIST architecture; BIST controller; IP cores; analysis; composite signature; design; fault coverage; intellectual property cores; lock-oriented design; modular logic built-in self-test; phase shifter; repeater; serial to parallel conversion; space-time test-response compactor; system integration; two-step development; Built-in self-test; Computational modeling; Design methodology; Intellectual property; Logic design; Performance evaluation; Phase shifters; Process design; Repeaters; Testing;
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5093-6
DOI :
10.1109/TEST.1998.743169
