Dual polycide gate and dual buried contact technologies achieving a 0.4 /spl mu/m nMOS/pMOS spacing for a 7.65 /spl mu/m/sup 2/ full-CMOS SRAM cell

Author

Koike, H. ; Unno, Y. ; Ishimaru, K. ; Matsuoka, F. ; Kakumu, M.

Author_Institution

Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

855

Lastpage

858

Abstract

An enlarged grain dual polycide gate and a dual buried contact technology using regrown amorphous-Si have been developed for high density full-CMOS SRAM cell. Lateral dopant diffusion has been suppressed to be less than 0.2 /spl mu/m, as a result, 0.4 /spl mu/m nMOS/pMOS spacing was realized using an 850/spl deg/C process. This technology can also achieve dual buried contact with low resistance and suppress gate depletion simultaneously. A 7.65 /spl mu/m/sup 2/ full-CMOS cell using 0.35 /spl mu/m design rule has been realized and superior cell stability at 1.5 V operation has been confirmed.<>

Keywords

CMOS memory circuits; SRAM chips; diffusion; grain size; integrated circuit metallisation; integrated circuit technology; 0.35 mum; 0.4 micron; 1.5 V; 850 C; Si; dual buried contact technology; dual polycide gate technology; enlarged grain; full-CMOS SRAM cell; gate depletion suppression; high density cell; lateral dopant diffusion; nMOS/pMOS spacing; regrown amorphous Si; static RAM; Absorption; Contact resistance; Grain boundaries; Impurities; Laboratories; MOS devices; Random access memory; Semiconductor devices; Silicides; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383278

Filename

383278