Title :
A 53µW −82dBm sensitivity 920MHz OOK receiver design using bias switch technique on 65nm SOTB CMOS technology
Author :
Hoang Minh Thien ; Sugii, N. ; Ishibashi, K.
Author_Institution :
Univ. of Electro-Commun., Chofu, Japan
Abstract :
This paper presents an ultra-low power receiver design at 920MHz. We proposed a receiver architecture, in which bias switch technique is applied to reduce power consumption significantly. The receiver was simulated and laid out on 65nm SOTB CMOS technology, consuming only 53μW at 0.6V supply voltage. It achieves a sensitivity of -82dBm with a data rate of 10 - 100 kbps.
Keywords :
CMOS integrated circuits; amplitude shift keying; low-power electronics; radio receivers; OOK receiver design; SOTB CMOS technology; bias switch technique; bit rate 10 kbit/s to 100 kbit/s; frequency 920 MHz; power 53 muW; power consumption reduction; size 65 nm; ultralow-power receiver design; voltage 0.6 V; CMOS integrated circuits; CMOS technology; Clocks; Power demand; Radio frequency; Receivers; Sensitivity; CMOS technology; OOK transceiver; SOTB; Ultra-low power receiver; wireless sensor;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE
Conference_Location :
Millbrae, CA
DOI :
10.1109/S3S.2014.7028185
