Title :
Switch-level bridging fault simulation in the presence of feedbacks
Author_Institution :
Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
Abstract :
This paper investigates the degradation in detectability of bridging faults caused by situations of active feedback and logically unresolvable intermediate values under different fault modeling assumptions. A bridging fault simulator is presented that is based on a combination of switch-level modeling and levelized logic simulation. Levelized simulation is efficient for fault propagation and feedback analysis, whereas the switch-level model is used for determining whether an intermediate value is logically resolvable. A method to extract the logic function of channel graphs is presented in order to perform levelized processing of switch-level networks. The experimental results show that active feedback may reduce fault coverage by as much as 9% for stuck-at test sets and realistic bridging fault sets
Keywords :
CMOS logic circuits; VLSI; circuit feedback; discrete event simulation; fault simulation; integrated circuit modelling; logic simulation; logic testing; short-circuit currents; CMOS gates; VLSI testability; active feedback; channel graphs; degradation in detectability; event-driven simulation; fault modeling assumptions; fault propagation; feedback analysis; levelized logic simulation; logic function extraction; logically unresolvable intermediate values; region of logic uncertainty; stuck-at test sets; switch-level bridging fault simulation; switch-level modeling; Bridge circuits; Circuit faults; Circuit testing; Computational modeling; Discrete event simulation; Feedback circuits; Feedback loop; Logic testing; Semiconductor device modeling; Voltage;
Conference_Titel :
Test Conference, 1998. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5093-6
DOI :
10.1109/TEST.1998.743175
