GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification

Hierarchy is key to managing design complexity. A hierarchical design system needs to maintain many views of the same design entity. Some of the examples might be physical view for placement routing and extraction; transistor schematic view for circuit simulation, timing characterization and noise analysis; a gate level schematic view for timing, verification, logic simulation, fault simulation and automatic lest pattern generation (ATPG); a register transfer level (RTL) view for specification and high level simulation etc. In order to achieve highest system performance, multiple design iterations are necessary, each iteration involving both forward and backward pass through hierarchy, with manual changes at any level of the hierarchy. This poses an essential challenge of keeping all views of same design entity in sync. In this paper we describe an automatic tool called GateMaker, that has been developed to extract a gate level schematic model from a transistor level schematic model for the purposes of logic simulation, fault simulation and automatic test pattern generation. This eliminates a manual process and offers manifold advantages that will be discussed in this paper