Efficient absolute difference circuits in Virtex-5 FPGAs

This paper presents a novel architecture optimized for realizing efficient absolute difference circuits in Virtex-5 FPGA devices. The proposed structure efficiently uses the 6-input look-up-tables available within the chosen devices family to maximize speed performance and to minimize the amount of occupied resources. In comparison with the DSP- and the LUT-based absolute difference circuits automatically synthesized and mapped by the ISE development tool the proposed structure is up to 40% cheaper and up to 61.5% faster.