Design driven patterning optimizations for low K1 lithography

Conventional resolution enhancement techniques (RET) are becoming increasingly inadequate at addressing the challenges of subwavelength lithography. However, the relentless pursuit of feature scaling can be continued for several more generations through increased co-optimization of design and process. A key enabler for such co-optimization is enhancement of design-manufacturing interface to allow more information than traditional layout shapes to be propagated to lithography. We describe a method to generate this additional information in the form of shape tolerances on layout polygons. We further propose an integrated model-based retargeting and optical proximity correction (OPC) flow to optimize lithographic process window in the presence of shape tolerances. Our simulation results show that this increased level of interaction between design and lithography can lead to fewer process hotspots on-wafer compared to conventional design-oblivious methods.