Self-Aligned LOCOS/Trench (SALOT) combination isolation technology planarized by chemical mechanical polishing

Author

Park, T. ; Ahn, S.J. ; Ko, J.H. ; Hong, C.G. ; Kim, J.D. ; Ahn, S.T. ; Lee, M.Y.

Author_Institution

Samsung Electron. Co. Ltd., Kyungki-Do, South Korea

fYear

1994

fDate

11-14 Dec. 1994

Firstpage

675

Lastpage

678

Abstract

A novel isolation technology of Self-Aligned LOCOS/Trench (SALOT) has been developed for the isolation of deep-sub micron devices. SALOT has the isolation structure of a Poly-Buffered LOCOS (PBL) field oxide and a self-aligned trench at the center of a narrow field region planarized by the Chemical Mechanical Polishing (CMP) process. With SALOT, dishing was effectively suppressed for field regions as wide as 4 mm. Devices with SALOT show excellent isolation characteristics and gate oxide quality, and low leakage currents. SALOT can be scaled down to the 1 Gbit DRAM generation.<>

Keywords

DRAM chips; MOS memory circuits; integrated circuit technology; isolation technology; leakage currents; polishing; 1 Gbit; 4 mm; DRAM; MOS process; SALOT; chemical mechanical polishing; deep-sub micron devices; gate oxide quality; isolation technology; leakage currents; narrow field region; poly-buffered LOCOS; self-aligned LOCOS/trench technology; Anisotropic magnetoresistance; Chemical technology; Chemical vapor deposition; Etching; Isolation technology; Lithography; Planarization; Random access memory; Shape; Silicon compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-2111-1

Type

conf

DOI

10.1109/IEDM.1994.383291

Filename

383291