• DocumentCode
    2525119
  • Title

    Design and implementation of the “G2” PowerPCTM 603e-embedded microprocessor core

  • Author

    Hunter, Craig ; Gaither, Justin

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • fYear
    1998
  • fDate
    18-23 Oct 1998
  • Firstpage
    473
  • Lastpage
    479
  • Abstract
    New and emerging demands in the embedded market has precipitated in the development of the “G2” PowerPC 603e microprocessor into a reusable hard core. The demands and requirements of an embedded core microprocessor require significant changes in the physical design, verification and test strategies. Reuse and standardization in design data and test data present new challenges for an existing family of microprocessors
  • Keywords
    automatic test pattern generation; boundary scan testing; design for testability; embedded systems; formal verification; hardware-software codesign; integrated circuit testing; microprocessor chips; reduced instruction set computing; ATPG model; G2 PowerPC 603e microprocessor; HyperMOS3; JTAG port; boundary scan circuitry; core integration; data reuse; data standardization; debug processor interface; design; embedded microprocessor core; implementation; pattern data format; power bussing; reusable hard core; superscalar processor; test strategies; verification strategies; Circuits; Clocks; Design optimization; Logic devices; Microprocessors; Power generation; Routing; Testing; Time to market; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1998. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-5093-6
  • Type

    conf

  • DOI
    10.1109/TEST.1998.743188
  • Filename
    743188
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2525119