Title :
Performance assessment of ULP analog/RF MOSFET architectures
Author :
Ghosh, D. ; Kranti, A.
Author_Institution :
Low Power Nanoelectron. Res. Group, Indian Inst. of Technol. Indore, Indore, India
Abstract :
Ultra low power (ULP) operation is increasingly in demand for future System-on-Chip (SOC) circuits using nanoscale analog/RF transistors. In this work, we analyze the analog/RF performance metrics of different ULP MOSFET architectures and quantify the advantages and challenges associated with underlap inversion-mode (INV), Junctionless (JL), lateral tunnel FET (LTFET) and vertical tunnel FET (VTFET) in terms of gain and bandwidth.
Keywords :
MOSFET; low-power electronics; system-on-chip; tunnel transistors; INV; JL; LTFET; SOC circuits; ULP analog-RF MOSFET architectures; VTFET; junctionless; lateral tunnel FET; nanoscale analog transistors; performance assessment; system-on-chip circuits; ultra low power operation; underlap inversion-mode; vertical tunnel FET; Doping; Gain; Hafnium compounds; Logic gates; MOSFET; Radio frequency; Tunneling;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE
Conference_Location :
Millbrae, CA
DOI :
10.1109/S3S.2014.7028199
