An optimal probing method of pre-bond TSV fault identification in 3D stacked ICs

Author

Bei Zhang ; Agrawal, V.D.

Author_Institution

Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA

fYear

2014

fDate

6-9 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

A fast TSV identification algorithm is proposed in this work to reduce the test time of pre-bond TSV probing. The speeding up of the algorithm comes from two aspects. First, any unnecessary session during the test is skipped. Second, the test terminates as soon as either all TSVs have been identified or a pre-specified maximum number of faulty TSVs have been identified. Experimental results demonstrate that instead of testing all sessions as stated in previous work, the algorithm always finishes the pre-bond TSV test after only a small portion of all sessions. The algorithm reduces pre-bond TSV test time and is expected to greatly reduce the pre-bond testing and the overall 3D device manufacturing costs.

Keywords

fault diagnosis; integrated circuit reliability; integrated circuit testing; three-dimensional integrated circuits; 3D device manufacturing costs; 3D stacked IC; optimal probing method; prebond TSV fault identification; prebond testing reduction; Circuit faults; Fault diagnosis; Needles; Probes; Testing; Three-dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE

Conference_Location

Millbrae, CA

Type

conf

DOI

10.1109/S3S.2014.7028201

Filename

7028201